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Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

Apr. 27 1997 to May 1 1997

Monterey, California

ISBN: 0-8186-7810-0

Table of Contents

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)Freely available from IEEE.pp. 0_5-0_5
ForewordFreely available from IEEE.pp. xiii
Steering CommitteeFreely available from IEEE.pp. xiv
Program CommitteeFreely available from IEEE.pp. xvi
Test Technology Technical CommitteeFreely available from IEEE.pp. xvii
Test Technology Technical Committee Sponsored MeetingsFreely available from IEEE.pp. xviii
ReviewersFreely available from IEEE.pp. xix
Best Paper Award 96Freely available from IEEE.pp. xxii
Best Panel Award 96Freely available from IEEE.pp. xxiii
Overview of TutorialsFreely available from IEEE.pp. xxiv
KEYNOTE ADDRESS
Current Trends and Future Directions in Test and DFTFull-text access may be available. Sign in or learn about subscription options.pp. xxx
by Gadi Singer, General Manager, Design Technology, Intel Corporation
INVITED TALK
Test and System Level IntegrationFull-text access may be available. Sign in or learn about subscription options.pp. xxxii
by Gary Smith, Principal Analyst Dataquest
SESSION 1: CORE & PROCESSOR TEST
1.1 Test methodology for embedded cores which protects intellectual propertyFull-text access may be available. Sign in or learn about subscription options.pp. 2
by K. De
SESSION 1: CORE & PROCESSOR TEST
Testing Embedded Cores Using Partial Isolation RingsFull-text access may be available. Sign in or learn about subscription options.pp. 10
by Nur A. Touba, Bahram Pouya
SESSION 1: CORE & PROCESSOR TEST
A practical approach to instruction-based test generation for functional modules of VLSI processorsFull-text access may be available. Sign in or learn about subscription options.pp. 17
by K. Hatayama, K. Hikone, T. Miyazaki, H. Yamada
SESSION 2: RAM TEST
Assessing SRAM test coverage for sub-micron CMOS technologiesFull-text access may be available. Sign in or learn about subscription options.pp. 24
by V. Kim, T. Chen
SESSION 2: RAM TEST
Experimental fault analysis of 1 Mb SRAM chipsFull-text access may be available. Sign in or learn about subscription options.pp. 31
by H. Goto, S. Nakamura, K. Iwasaki
SESSION 2: RAM TEST
Disturb Neighborhood Pattern Sensitive FaultFull-text access may be available. Sign in or learn about subscription options.pp. 37
by A.J. van de Goor, I.B.S. Tlili
SESSION 3: BIST I
Methods to reduce test application time for accumulator-based self-testFull-text access may be available. Sign in or learn about subscription options.pp. 48
by A.P. Stroele, F. Mayer
SESSION 3: BIST I
Implicit test pattern generation constrained to cellular automata embeddingFull-text access may be available. Sign in or learn about subscription options.pp. 54
by F. Fummi, D. Sciuto
Cellular automata for deterministic sequential test pattern generationFull-text access may be available. Sign in or learn about subscription options.pp. 60-65
by S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda
SESSION 4: CURRENT TESTING TECHNIQUES
Bridges in sequential CMOS circuits: current-voltage signatureFull-text access may be available. Sign in or learn about subscription options.pp. 68
by R. Rodriguez-Montanes, J. Figueras
SESSION 4: CURRENT TESTING TECHNIQUES
Using fault sampling to compute I/sub DDQ/ diagnostic test setsFull-text access may be available. Sign in or learn about subscription options.pp. 74
by Yiming Gong, S. Chakravarty
SESSION 4: CURRENT TESTING TECHNIQUES
A novel probabilistic approach for IC diagnosis based on differential quiescent current signaturesFull-text access may be available. Sign in or learn about subscription options.pp. 80
by C. Thibeault
SESSION 5: DELAY TEST & DIAGNOSIS
High Quality Robust Tests for Path Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 88
by Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
SESSION 5: DELAY TEST & DIAGNOSIS
An optimized BIST test pattern generator for delay testingFull-text access may be available. Sign in or learn about subscription options.pp. 94
by P. Girard, C. Landrault, V. Moreda, S. Pravossoudovitch
SESSION 5: DELAY TEST & DIAGNOSIS
On the Fault Coverage of Interconnect DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 101
by X.T. Chen, F.J. Meyer, F. Lombardi
SESSION 6: FAULT MODELING & PARAMETRIC TEST
Analysis of Ground Bounce in Deep Sub-Micron CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 110
by Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
SESSION 6: FAULT MODELING & PARAMETRIC TEST
Switch-level modeling of feedback faults using global oscillation controlFull-text access may be available. Sign in or learn about subscription options.pp. 117
by P. Dahlgren
SESSION 6: FAULT MODELING & PARAMETRIC TEST
Built-in parametric test for controlled impedance I/OsFull-text access may be available. Sign in or learn about subscription options.pp. 123
by T. Haulin
SESSION 7: VERIFICATION & DEBUGGING
Using ATPG for clock rules checking in complex scan designsFull-text access may be available. Sign in or learn about subscription options.pp. 130
by P. Wohl, J. Waicukauski
SESSION 7: VERIFICATION & DEBUGGING
A Novel Solution for Chip-Level Functional Timing VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 137
by Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham
SESSION 7: VERIFICATION & DEBUGGING
Incremental logic rectificationFull-text access may be available. Sign in or learn about subscription options.pp. 143
by Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
SESSION 7: VERIFICATION & DEBUGGING
Polynomial Formal Verification of MultipliersFull-text access may be available. Sign in or learn about subscription options.pp. 150
by Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
SESSION 8: ANALOG TEST 1
CLP-based Multifrequency Test Generation for Analog CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 158
by A. Abderrahman, E. Cerny, B. Kaminska
SESSION 8: ANALOG TEST 1
Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 166
by Karim Arabi, Bozena Kaminska
SESSION 8: ANALOG TEST 1
Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 172
by Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz
SESSION 8: ANALOG TEST 1
Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMSFull-text access may be available. Sign in or learn about subscription options.pp. 177
by N.J. Godambe, C.-J.R. Shi
PANEL SESSION 1:
Systems On Silicon: Design and Test ChallengesFull-text access may be available. Sign in or learn about subscription options.pp. 184
PANEL SESSION 2
Will 0.1um Digital Circuits Require Mixed-Signal TestingFull-text access may be available. Sign in or learn about subscription options.pp. 186
SESSION 9: SEQUENTIAL CIRCUITS TEST I
Fast Algorithms for Static Compaction of Sequential Circuit Test VectorsFull-text access may be available. Sign in or learn about subscription options.pp. 188
by Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
SESSION 9: SEQUENTIAL CIRCUITS TEST I
Diagnostic Test Pattern Generation for Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 196
by Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs, hartanto@dtc.hp. com
SESSION 9: SEQUENTIAL CIRCUITS TEST I
Critical hazard free test generation for asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 203
by A. Khoche, E. Brunvand
SESSION 10: CONCURRENT CHECKING
Highly testable and compact single output comparatorFull-text access may be available. Sign in or learn about subscription options.pp. 210
by C. Metra, M. Favalli, B. Ricco
SESSION 10: CONCURRENT CHECKING
Self-exercising self testing k-order comparatorsFull-text access may be available. Sign in or learn about subscription options.pp. 216
by X. Kavousianos, D. Nikolos
SESSION 10: CONCURRENT CHECKING
Exact probabilistic analysis of error detection for parity checkersFull-text access may be available. Sign in or learn about subscription options.pp. 222
by V.A. Vardanian
SESSION 11: TEST OF REGULAR STRUCTURES
Test of RAM-based FPGA: methodology and application to the interconnectFull-text access may be available. Sign in or learn about subscription options.pp. 230
by M. Renovell, J. Figueras, Y. Zorian
SESSION 11: TEST OF REGULAR STRUCTURES
Robust Sequential Fault Testing of Iterative Logic ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 238
by Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis
SESSION 11: TEST OF REGULAR STRUCTURES
A new approach for testing artificial neural networksFull-text access may be available. Sign in or learn about subscription options.pp. 245
by C.A. Fleischer, L.A. Belfore, II
SESSION 12: ANALOG TEST II
Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 252
by Christian Dufaza, Hassan Ihs
SESSION 12: ANALOG TEST II
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response samplingFull-text access may be available. Sign in or learn about subscription options.pp. 261
by P.N. Variyam, A. Chatterjeee, N. Nagi
SESSION 12: ANALOG TEST II
Functional test pattern generation for CMOS operational amplifierFull-text access may be available. Sign in or learn about subscription options.pp. 267
by Soon Jyh Chang, Chung Len Lee, Jwu E Chen
SESSION 13: FAULT SIMULATION AND REDUNDANCY IDENTIFICATION
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulationFull-text access may be available. Sign in or learn about subscription options.pp. 274
by D. Krishnaswamy, E.M. Rudnick, J.H. Patel, P. Banerjee
SESSION 13: FAULT SIMULATION AND REDUNDANCY IDENTIFICATION
The Dynamic Rollback Problem in Concurrent Event-Driven Fault SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 282
by Laura Farinetti, Pier Luca Montessoro
SESSION 13: FAULT SIMULATION AND REDUNDANCY IDENTIFICATION
Static logic implication with application to redundancy identificationFull-text access may be available. Sign in or learn about subscription options.pp. 288
by J.-K. Zhao, E.M. Rudnick, J.H. Patel
SESSION 14: MIXED SIGNAL TEST
Automated test pattern generation for analog integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 296
by W. Verhaegen, G. Van der Plas, G. Gielen
SESSION 14: MIXED SIGNAL TEST
A DFT Technique for Analog-to-Digital Converters with digital correctionFull-text access may be available. Sign in or learn about subscription options.pp. 302
by Eduardo Peralias, Adoracion Rueda, Jose L. Huertas
SESSION 14: MIXED SIGNAL TEST
Determination of coherence errors in ADC spectral domain testingFull-text access may be available. Sign in or learn about subscription options.pp. 308
by W.D. Bartlett
PANEL SESSION 3:
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testingFull-text access may be available. Sign in or learn about subscription options.pp. 459
by P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken
PANEL SESSION 4:
ATE for VLSI: What Challenges Lie Ahead?Full-text access may be available. Sign in or learn about subscription options.pp. 318
PANEL SESSION 5:
Hardware Test: Can We Learn from Software Testing?Full-text access may be available. Sign in or learn about subscription options.pp. 320
SESSION 15: SEQUENTIAL CIRCUITS TEST II
Testability of Sequential Circuits with Multi-Cycle False PathsFull-text access may be available. Sign in or learn about subscription options.pp. 322
by Priyank Kalla, Maciej Ciesielski
SESSION 15: SEQUENTIAL CIRCUITS TEST II
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverageFull-text access may be available. Sign in or learn about subscription options.pp. 329
by I. Pomeranz, S.M. Reddy
SESSION 15: SEQUENTIAL CIRCUITS TEST II
On n-detection test sequences for synchronous sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 336
by I. Pomeranz, S.M. Reddy
SESSION 16: ON-LINE TESTING AND FAULT-TOLERANT DESIGN
An on-line testable UART implemented using IFISFull-text access may be available. Sign in or learn about subscription options.pp. 344
by J. Yeandel, D. Thulborn, S. Jones
SESSION 16: ON-LINE TESTING AND FAULT-TOLERANT DESIGN
A linear code-preserving signature analyzer COPMISRFull-text access may be available. Sign in or learn about subscription options.pp. 350
by A. Hlawiczka, M. Gossel, E.S. Sogormonyan
SESSION 16: ON-LINE TESTING AND FAULT-TOLERANT DESIGN
A high-level synthesis approach to design of fault-tolerant systemsFull-text access may be available. Sign in or learn about subscription options.pp. 356
by G. Buonanno, M. Pugassi, M.G. Sami
SESSION 17: SCAN AND BOUNDARY SCAN
ATPG for scan chain latches and flip-flopsFull-text access may be available. Sign in or learn about subscription options.pp. 364
by S.R. Maka, E.J. McCluskey
SESSION 17: SCAN AND BOUNDARY SCAN
High-Level Synthesis for Orthogonal ScanFull-text access may be available. Sign in or learn about subscription options.pp. 370
by Robert B. Norwood, Edward J. McCluskey
SESSION 17: SCAN AND BOUNDARY SCAN
BIST TPGs for Faults in Board Level Interconnect via Boundary ScanFull-text access may be available. Sign in or learn about subscription options.pp. 376
by Chen-Huan Chiang, Sandeep K. Gupta
SESSION 18: TESTABILITY ANALYSIS
A methodolgy for characterizing cell testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 384
by A. Jee, F.J. Ferguson
SESSION 18: TESTABILITY ANALYSIS
Fault coverage of a long random test sequence estimated from a short simulationFull-text access may be available. Sign in or learn about subscription options.pp. 391
by V. Prepin, R. David
SESSION 18: TESTABILITY ANALYSIS
Random pattern testability of memory control logicFull-text access may be available. Sign in or learn about subscription options.pp. 399
by J. Savir
SESSION 19: BIST II
Obtaining High Fault Coverage with Circular BIST Via State SkippingFull-text access may be available. Sign in or learn about subscription options.pp. 410
by Nur A. Touba
SESSION 19: BIST II
Salvaging test windows in BIST diagnosticsFull-text access may be available. Sign in or learn about subscription options.pp. 416
by J. Savir
SESSION 19: BIST II
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 426
by Can Oekmen, Martin Keim, Rolf Krieger, Bernd Becker
SESSION 20: THERMAL & ELEVATED VOLTAGE TESTING
Differential Sensing Strategy for Dynamic Thermal Testing of ICsFull-text access may be available. Sign in or learn about subscription options.pp. 434
by Josep Altet, Antonio Rubio
SESSION 20: THERMAL & ELEVATED VOLTAGE TESTING
Integrating on-chip temperature sensors into DfT schemes and BIST architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 440
by V. Szekely, M. Rencz, B. Courtois
SESSION 20: THERMAL & ELEVATED VOLTAGE TESTING
SHOrt voltage elevation (SHOVE) test for weak CMOS ICsFull-text access may be available. Sign in or learn about subscription options.pp. 446
by J.T.Y. Chang, E.J. McCluskey
PANEL SESSION 7:
Power Dissipation During Testing: Should We Worry About it?Full-text access may be available. Sign in or learn about subscription options.pp. 456
PANEL SESSION 8:
Microprocessor Test and Validation: Any New Avenues?Full-text access may be available. Sign in or learn about subscription options.pp. 458
PANEL SESSION 8:
Author IndexFreely available from IEEE.pp. 465
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