Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)
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Abstract

This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, "Semiconductor Test Method Evaluation ").
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