Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits

T. Lee; I.N. Hajj; E.M. Rudnick; J.H. Patel

doi:10.1109/VTEST.1996.510893

Proceedings of 14th VLSI Test Symposium

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits

Year: 1996, Pages: 456

DOI Bookmark: 10.1109/VTEST.1996.510893

Authors

T. Lee, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
I.N. Hajj, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
E.M. Rudnick, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA
J.H. Patel, Gen. Syst. Lab., Hewlett-Packard Co., Roseville, CA, USA

Abstract

An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. An adaptive genetic algorithm (GA) is used to generate compact test sets. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that GA-based test generators are very well suited for generating compact test sets for I/sub DDQ/ testing of bridging faults.

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