Abstract
The design and implementation of a fast, easily testable arithmetic-logic unit (ALU) is described. It is built around an adder design which is level-testable (L-testable), implying that the number of test patterns required to detect all functional faults in modules grows logarithmically with the size of the ALU. L-testability is achieved by exploiting some inherent properties of carry-lookahead addition. The resulting ALU design requires only two extra inputs, regardless of the size of the ALU. For an 8-bit implementation that has little impact on performance, the area overhead is shown to be less than 9%.