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Proceedings 13th IEEE VLSI Test Symposium

Apr. 30 1995 to May 3 1995

Princeton, New Jersey

ISBN: 0-8186-7000-2

Table of Contents

Proceedings 13th IEEE VLSI Test SymposiumFreely available from IEEE.pp. iii-iii
ForewordFreely available from IEEE.pp. xii
Steering CommitteeFreely available from IEEE.pp. xiii
Advisory CommitteeFreely available from IEEE.pp. xiv
Program CommitteeFreely available from IEEE.pp. xv
ReviewersFreely available from IEEE.pp. xvi
Best Paper AwardFreely available from IEEE.pp. xx
Session 1: Advanced Test Pattern Generation Methods
Identifying sequentially untestable faults using illegal statesFull-text access may be available. Sign in or learn about subscription options.pp. 0004
by D.E. Long, M.A. Iyer, M. Abramovici
Session 1: Advanced Test Pattern Generation Methods
Redundancy Removal and Test Generation for Circuits with Non-Boolean PrimitivesFull-text access may be available. Sign in or learn about subscription options.pp. 0012
by Srimat T. Chakradhar, Steven G. Rothweiler
Session 1: Advanced Test Pattern Generation Methods
High-level test generation using physically-induced faultsFull-text access may be available. Sign in or learn about subscription options.pp. 0020
by M.C. Hansen, J.P. Hayes
Session 1: Advanced Test Pattern Generation Methods
A portable ATPG tool for parallel and distributed systemsFull-text access may be available. Sign in or learn about subscription options.pp. 0029
by F. Corno, P. Prinetto, M. Rebaudengo, M.S. Reorda, E. Veiluva
Session 1: Advanced Test Pattern Generation Methods
Testing combinational iterative logic arrays for realistic faultsFull-text access may be available. Sign in or learn about subscription options.pp. 0035
by D. Gizopoulos, D. Nikolos, A. Paschalis
Session 2: Mixed-Signal Circuit Test
Verification of transient response of linear analog circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0042
by A. Balivada, Y. Hoskote, J.A. Abraham
Session 2: Mixed-Signal Circuit Test
A solution for the on-line test of analog ladder filtersFull-text access may be available. Sign in or learn about subscription options.pp. 0048
by D. Vazquez, A. Rueda, J.L. Huertas
Session 2: Mixed-Signal Circuit Test
Frequency-based BIST for analog circuit testingFull-text access may be available. Sign in or learn about subscription options.pp. 0054
by S. Khaled, B. Kaminska, B. Courtois, M. Lubaszewski
Session 2: Mixed-Signal Circuit Test
A low cost 100 MHz analog test busFull-text access may be available. Sign in or learn about subscription options.pp. 0060
by S. Sunter
Session 2: Mixed-Signal Circuit Test
Self-test in a VCM driver chipFull-text access may be available. Sign in or learn about subscription options.pp. 0066
by L. Sebaa, N. Gardner, R. Neidorff, R. Valley
Session 3: Defect Coverage and Test Quality
On the decline of testing efficiency as fault coverage approaches 100%Full-text access may be available. Sign in or learn about subscription options.pp. 0074
by L.-C. Wang, P.R. Mercer, S.W. Kao, T.W. Williams
Session 3: Defect Coverage and Test Quality
The use of IDDQ testing in low stuck-at coverage situationsFull-text access may be available. Sign in or learn about subscription options.pp. 0084
by P.C. Maxwell
Session 3: Defect Coverage and Test Quality
Cyclic stress tests for full scan circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 89-94
by V. Dabholkar, S. Chakravarty, J. Najm, J. Patel
Session 3: Defect Coverage and Test Quality
An approach to dynamic power consumption current testing of CMOS ICsFull-text access may be available. Sign in or learn about subscription options.pp. 0095
by J.A. Segura, M. Roca, D. Mateo, A. Rubio
Session 3: Defect Coverage and Test Quality
Iddt testing of continuous-time filtersFull-text access may be available. Sign in or learn about subscription options.pp. 0101
by J. Arguelles, M.J. Lopez, J. Blanco, M. Martinez, S. Bracho
Session 4: Advanced BIST Approaches
On shrinking wide compressorsFull-text access may be available. Sign in or learn about subscription options.pp. 0108
by J. Savir
Session 4: Advanced BIST Approaches
Signature analysis and aliasing for sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0118
by A.P. Stroele
Session 4: Advanced BIST Approaches
An apparatus for pseudo-deterministic testingFull-text access may be available. Sign in or learn about subscription options.pp. 0125
by S.K. Mukund, E.J. McCluskey, T.R.N. Rao
Session 4: Advanced BIST Approaches
Arithmetic built-in self test for high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 0132
by N. Mukherjee, H. Kassab, J. Rajski, J. Tyszer
Session 4: Advanced BIST Approaches
Real-time on-board bus testingFull-text access may be available. Sign in or learn about subscription options.pp. 0140
by J.A. Floyd, M. Perry
Session 5: Synthesis for Testability
Resynthesis for sequential circuits designed with a specified initial stateFull-text access may be available. Sign in or learn about subscription options.pp. 0152
by H. Yotsuyanagi, S. Kajihara, K. Kinoshita
Session 5: Synthesis for Testability
A distance reduction approach to design for testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 0158
by F.F. Hsu, J.H. Patel
Session 5: Synthesis for Testability
An optimized testable architecture for finite state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 0164
by Ting-Yu Kuo, Chun-Yeh Liu, K.K. Saluja
Session 5: Synthesis for Testability
Testability metrics for synthesis of self-testable designs and effective test plansFull-text access may be available. Sign in or learn about subscription options.pp. 0170
by K. Vahidi, A. Orailoglu
Session 5: Synthesis for Testability
RT level testability-driven partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 0176
by Xinli Gu
Session 6: Fault Modeling
The concept of resistance interval: a new parametric model for realistic resistive bridging faultFull-text access may be available. Sign in or learn about subscription options.pp. 0184
by M. Renovell, P. Huc, Y. Bertrand
Session 6: Fault Modeling
High level fault modeling of asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0190
by Ding Lu, C.Q. Tong
Session 6: Fault Modeling
Checking experiments to test latchesFull-text access may be available. Sign in or learn about subscription options.pp. 0196
by S.R. Makar, E.J. McCluskey
Session 6: Fault Modeling
Testability of floating gate defects in sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0202
by V.H. Champac, J. Figueras
Session 6: Fault Modeling
Switch-level modeling of transistor-level stuck-at faultsFull-text access may be available. Sign in or learn about subscription options.pp. 0208
by P. Liden, P. Dahlgren
Session 7: Fault Simulation I
Simulation of at-speed tests for stuck-at faultsFull-text access may be available. Sign in or learn about subscription options.pp. 0216
by T.J. Chakraborty, V.D. Agrawal
Session 7: Fault Simulation I
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0221
by R. Nair, Dong Sam Ha
Session 7: Fault Simulation I
Fault coverage analysis of RAM test algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 0227
by M. Riedel, J. Rajski
Session 7: Fault Simulation I
Reliability evaluation of combinational logic circuits by symbolic simulationFull-text access may be available. Sign in or learn about subscription options.pp. 0235
by A. Bogliolo, M. Damiani, P. Olivo, B. Ricco
Session 8: Fault Diagnosis
Improving the efficiency of error identification via signature analysisFull-text access may be available. Sign in or learn about subscription options.pp. 0244
by C.E. Stroud, T.R. Damarla
Session 8: Fault Diagnosis
Diagnosis of scan path failuresFull-text access may be available. Sign in or learn about subscription options.pp. 0250
by S. Edirisooriya, G. Edirisooriya
Session 8: Fault Diagnosis
Diagnosis of interconnects and FPICs using a structured walking-1 approachFull-text access may be available. Sign in or learn about subscription options.pp. 0256
by T. Liu, F. Lombardi, J. Salinas
Session 8: Fault Diagnosis
Detection and location of faults and defects using digital signal processingFull-text access may be available. Sign in or learn about subscription options.pp. 0262
by C. Thibeault
Session 9: Design for Testability
Asynchronous multiple scan chainsFull-text access may be available. Sign in or learn about subscription options.pp. 0270
by S. Narayanan, M.A. Breuer
Session 9: Design for Testability
Partial scan designs without using a separate scan clockFull-text access may be available. Sign in or learn about subscription options.pp. 0277
by Kwang-Ting Cheng
Session 9: Design for Testability
A partial scan methodology for testing self-timed circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0283
by A. Khoche, E. Brunvand
Session 9: Design for Testability
On the design of at-speed testable VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0290
by M. Soufi, Y. Savaria, B. Kaminska
Session 9: Design for Testability
Scan testing of micropipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 0296
by O.A. Petlin, S.B. Furber
Session 10: Iddq Testing
Test pattern generation for I/sub DDQ/: increasing test qualityFull-text access may be available. Sign in or learn about subscription options.pp. 0304
by M. Dalpasso, M. Favalli, P. Olivo
Session 10: Iddq Testing
Compact test generation for bridging faults under I/sub DDQ/ testingFull-text access may be available. Sign in or learn about subscription options.pp. 0310
by R.S. Reddy, I. Pomeranz, S.M. Reddy, S. Kajihara
Session 10: Iddq Testing
CURRENT: a test generation system for I/sub DDQ/ testingFull-text access may be available. Sign in or learn about subscription options.pp. 0317
by U. Mahlstedt, J. Alt, M. Heinitz
Session 10: Iddq Testing
Detecting I/sub DDQ/ defective CMOS circuits by depoweringFull-text access may be available. Sign in or learn about subscription options.pp. 0324
by J. Rius, J. Figueras
Session 10: Iddq Testing
Test preparation for high coverage of physical defects in CMOS digital ICsFull-text access may be available. Sign in or learn about subscription options.pp. 0330
by M.B. Santos, M. Simoes, I. Teixeira, J.P. Teixeira
Improving topological ATPG with symbolic techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 338-343
by F. Corno, P. Prinetto, M. Sonza Reorda, U. Glaser, H.T. Vierhaus
Session 11: Automatic Test Pattern Generation
A scheduling problem in test generationFull-text access may be available. Sign in or learn about subscription options.pp. 0344
by T. Inoue, H. Maeda, H. Fujiwara
Session 11: Automatic Test Pattern Generation
Detectable perturbations: a paradigm for technology-specific multi-fault test generationFull-text access may be available. Sign in or learn about subscription options.pp. 0350
by A. Zemva, F. Brglez
Session 11: Automatic Test Pattern Generation
Compact test sets for industrial circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0358
by M.H. Konijnenburg, J.T. van der Linden, A.J. van de Goor
Session 11: Automatic Test Pattern Generation
Reducing test application time in scan design schemesFull-text access may be available. Sign in or learn about subscription options.pp. 0367
by B. Vinnakota, N.J. Stessman
Session 12: Delay Fault Testing
Generation of high quality tests for functional sensitizable pathsFull-text access may be available. Sign in or learn about subscription options.pp. 0374
by A. Krstic, Kwang-Ting Cheng
Session 12: Delay Fault Testing
Diagnostic of path and gate delay faults in non-scan sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0380
by P. Girard, C. Landrault, S. Pravossoudovitch, B. Rodriguez
Session 12: Delay Fault Testing
On the application of local circuit transformations with special emphasis on path delay fault testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 0387
by H. Hengster, R. Drechsler, B. Becker
Session 12: Delay Fault Testing
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programmingFull-text access may be available. Sign in or learn about subscription options.pp. 0393
by I.P. Shaik, M.L. Bushnell
Session 12: Delay Fault Testing
Multifault testability of delay-testable circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0400
by W. Ke, P.R. Menon
Session 13: Test Pattern Generation for BIST
Transformed pseudo-random patterns for BISTFull-text access may be available. Sign in or learn about subscription options.pp. 0410
by N.A. Touba, E.J. McCluskey
Session 13: Test Pattern Generation for BIST
A novel pattern generator for near-perfect fault-coverageFull-text access may be available. Sign in or learn about subscription options.pp. 0417
by M. Chatterjee, D.K. Pradhan
Session 13: Test Pattern Generation for BIST
Decompression of test data using variable-length seed LFSRsFull-text access may be available. Sign in or learn about subscription options.pp. 0426
by N. Zacharia, J. Rajski, J. Tyszer
Session 13: Test Pattern Generation for BIST
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 0434
by S. Lejmi, B. Kaminska, B. Ayari
Session 13: Test Pattern Generation for BIST
Synthesis of locally exhaustive test pattern generatorsFull-text access may be available. Sign in or learn about subscription options.pp. 0440
by G. Kemnitz
Session 14: Self-Checking Systems I
An approach for system tests design and its applicationFull-text access may be available. Sign in or learn about subscription options.pp. 0448
by S.K. Shoukourian, A.G. Kostanian, V.A. Margarian, A.A. Ashour
Session 14: Self-Checking Systems I
Synthesis of combinational circuits with special fault-handling capabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 0454
by A. Bogliolo, M. Damiani
Session 14: Self-Checking Systems I
A tool for automatic generation of self-checking data pathsFull-text access may be available. Sign in or learn about subscription options.pp. 0460
by B. Hamdi, H. Bederr, M. Nicolaidis
Session 14: Self-Checking Systems I
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniersFull-text access may be available. Sign in or learn about subscription options.pp. 0467
by S. Brown, G. Gutierrez, R. Nelson, C. VanKrevelen
Session 14: Self-Checking Systems I
An experimental evaluation of the differential BICS for I/sub DDQ/ testingFull-text access may be available. Sign in or learn about subscription options.pp. 0472
by W.W. Weber, A.D. Singh
Best Paper - 1994
Structural constraints for circular self-test pathsFull-text access may be available. Sign in or learn about subscription options.pp. 0486
by J. Carletta, C. Papachristou
Best Paper - 1994
Author IndexFreely available from IEEE.pp. 0492
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