Published Articles >> Table of Contents >> Abstract

13th IEEE VLSI Test Symposium (VTS'95)   p. 0434
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits
S. Lejmi, Ecole Polytech. de Montreal, Que., Canada
B. Kaminska, Ecole Polytech. de Montreal, Que., Canada
B. Ayari, Ecole Polytech. de Montreal, Que., Canada

Full Article Text:

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512671
Send link to a friend

Abstract
Abstract: In pseudo-exhaustive testing, the partitioning technique consists of placing segmentation cells in an acyclic sequential circuit in order to reduce the size of cones. These segmentations, which are transparent in normal mode and active during test mode, result in an overhead for the circuit. However, cutting edges containing registers eliminates these secondary effects. In this paper, we present a new approach to the partitioning problem of the synchronous sequential circuits based on the retiming technique. This approach consists in choosing a set of segmentation edges such that there exists a retiming minimizing the number of segmentation cells in the retimed circuit. Thus, for a given size limit of cone, we propose an iterative algorithm for pseudo-exhaustive sequential testing which combines our method with existing approaches. In addition, we prove that the proposed retiming can be considered as a peripheral retiming while at the same time integrating the logic optimization part in the partitioning process. Experimental results on the benchmark sequential circuits show that our approach significantly optimizes the retimed circuit and reduces the number of segmentation cells required in the original circuit.
Back to Top Additional Information
Index Terms- logic testing; sequential circuits; timing; logic partitioning; circuit optimisation; circuit analysis computing; iterative methods; retiming; resynthesis; partitioning; pseudo-exhaustive testing; sequential circuits; segmentation cells; synchronous circuits; segmentation edges; iterative algorithm; logic optimization Citation:  S. Lejmi, B. Kaminska, B. Ayari, "Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits," vts, p. 0434,  13th IEEE VLSI Test Symposium (VTS'95),  1995