| Abstract |
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Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to their ability to achieve near Shannon-limit communication channel capacity, the computational complexity of the decoder is a major concern. LDPC decoding consists of a series of iterative computations derived from a message-passing bipartite graph. In order to efficiently support the communication intensive nature of this application, we present a LDPC decoder architecture based on a network-on-chip communication fabric that provides a 1.2Gbps decoded throughput rate for a 3/4 code rate, 1024-bit block LDPC code. The proposed architecture can be reconfigured to support other LDPC codes of different block sizes and code rates. We also propose two novel power-aware optimizations that reduce the power consumption by up to 30%.
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 Additional Information
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Citation:
T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin,
"Implementing LDPC Decoding on Network-on-Chip,"
vlsid,
pp. 134-137,
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05),
2005
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