A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05) pp. 130-133
A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs
Ashok Narasimhan, State University of New York at Buffalo
Shantanu Divekar, State University of New York at Buffalo
Praveen Elakkumanan, State University of New York at Buffalo
Ramalingam Sridhar, State University of New York at Buffalo

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.18
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Abstract
Performance of System-on-Chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-Chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasi-synchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18µm technology.
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Citation: Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar, "A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs," vlsid, pp. 130-133, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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