Abstract
ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and fall delays that are dependent on process, voltage, and temperature variations across different dies on a wafer and within a die. A test engineer must verify the vectors for timing correctness before they are handed off to the product engineer. Currently, validation of test vectors is done using dynamic simulation of the circuit using the test vectors. A test vector is invalidated if it cannot reliably distinguish between a good and a faulty circuit under the signal placement and observation error window of the tester equipment. As chips become faster, the need to test them at their intended speed of operation has been recognized; accordingly, at-speed functional tests, memory BIST, and transition delay tests are being used for modern ASICs. Since structural tests can result in much more switching activity in the circuit than what is estimated during normal functioning, they may fail delay testing due to nanometer effects such as crosstalk and IR drop. As a result, the validation performed by a dynamic simulation can be prone to error. Here is a case of a test that over-exercises the chip and declares it faulty even when the chip may work correctly in functional mode at the intended speed. One solution to this problem is to overdesign, e.g. oversize the power rails or increase wiring pitch, but this will impact the yield of the product. We propose layout-aware verification of at-speed test vectors and eliminating test vectors that can result in misclassification. Attempting to address this verification in dynamic simulation will force the use of circuit simulation or mixed-level simulation techniques, which are expensive in terms of run time. We discuss a static approach to validate the test vectors to save valuable cycle time. Experimental results on two designs will be presented to illustrate our approach.