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Published Articles >> Table of Contents >> Abstract
17th International Conference on VLSI Design
p. 455
On Buffering Schemes for Long Multi-Layer Nets
Vani Prasad, Indian Institute of Technology, Bombay
Madhav P. Desai, Indian Institute of Technology, Bombay
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260964
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We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution for the two layer case. This exact solution, however, is irregular and dependent on the length of the net. We look for approximate solutions which are not only regular but are independent of the length of the net. We show that two of these approximate solutions yield delays that are within a constant of the optimal solution. We have seen that our results hold true even for the three-layer case. We conjecture that our models can be inductively extended for multi-layer nets as well.
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Citation:
Vani Prasad, Madhav P. Desai,
"On Buffering Schemes for Long Multi-Layer Nets,"
vlsid,
p. 455,
17th International Conference on VLSI Design,
2004
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