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Published Articles >> Table of Contents >> Abstract
17th International Conference on VLSI Design
p. 195
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization
Ashok K. Murugavel, University of South Florida, Tampa
N. Ranganathan, University of South Florida, Tampa
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260924
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In this paper, we propose new algorithms for gate sizing and buffer insertion that aim at reducing the switched capacitance in gate level circuits. We have formulated the gate sizing and the buffer insertion problems as competitive resource allocation based auction theoretic games and develop solutions based on the Nash equilibrium function. The main contribution of this work is in the application of economic models and game theoretic solutions to logic synthesis problems for power optimization. The gate sizing problem is modeled as a Progressive Second Price (PSP) auction, where the players of the auction (representing the gates) bid for partial delays in each path of the circuit. The PSP auction process attempts to optimize the power consumption of each path in the circuit. The bids supplied by the players are used to determine the allocation for each player in the auction, using a game theoretic formulation. The size of a gate is determined based on its delay allocation. The gate sizing problem can be integrated with buffer insertion for better power optimization and we develop a game theoretic algorithm for combined gate sizing and buffer insertion. Experimental results on MCNC '91 benchmark circuits indicate that the proposed algorithms provide better power optimization than similar approaches in the literature, and are comparable in terms of run times.
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Citation:
Ashok K. Murugavel, N. Ranganathan,
"Gate Sizing and Buffer Insertion using Economic Models for Power Optimization,"
vlsid,
p. 195,
17th International Conference on VLSI Design,
2004
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