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Published Articles >> Table of Contents >> Abstract
17th International Conference on VLSI Design
p. 85
Synthesis of Low Power High Performance Dual-VT PTL Circuits
Debasis Samanta, North Eastern Regional Institute of Science & Technology
Ajit Pal, Indian Institute of Technology Kharagpur
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260907
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Although major portion of power dissipation in present generation CMOS circuits (250nm - 180nm) is due to charging and discharging of various node capacitors, known as switching power, the leakage power is becoming more and more predominant in ultra-deep submicron (UDSM) technologies. In pass-transistor logic (PTL) circuits, the output of each PTL cell is provided with a buffer to reduce delay and restore voltage level. These buffers, in turn, are the primary source of leakage power in PTL circuits. In this paper we have proposed, for the first time, the use of transistors of two threshold voltages (dual-VT) to minimize leakage power. We have extended our existing algorithm for logic synthesis of dual-VT PTL circuits. The extended algorithm has been tested for a large number of ISCAS benchmark circuits. Experimental results show that the use of dual-VT leads to a reduction in leakage power of about 45% in active mode and 76% in standby mode compared to their single-VT realization. Moreover, total power dissipation reduces by 18% with respect to single-VT realizations.
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Citation:
Debasis Samanta, Ajit Pal,
"Synthesis of Low Power High Performance Dual-VT PTL Circuits,"
vlsid,
p. 85,
17th International Conference on VLSI Design,
2004
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