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Published Articles >> Table of Contents >> Abstract
17th International Conference on VLSI Design
p. 30
CMOS Scaling for sub-90 nm to sub-10 nm
Hiroshi Iwai, Tokyo Institute of Technology
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260899
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Recently, CMOS downsizing has been accelerated very aggressively in both production and reseach level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation.
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Citation:
Hiroshi Iwai,
"CMOS Scaling for sub-90 nm to sub-10 nm,"
vlsid,
p. 30,
17th International Conference on VLSI Design,
2004
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