|
Published Articles >> Table of Contents >> Abstract
16th International Conference on VLSI Design
p. 395
CMOS Digital Imager Design from a System-on-a-chip Perspective
Bedabrata Pain, California Institute of Technology
Bruce Hancock, California Institute of Technology
Thomas Cunningham, California Institute of Technology
Guang Yang, California Institute of Technology
Suresh Seshadri, California Institute of Technology
Julie Heynssens, California Institute of Technology
Chris Wrigley, California Institute of Technology
Full Article Text:
  
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183168
Send link to a friend
| Abstract |
|
Due to substantial mixed analog-digital circuit integration in one chip, CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binary-scaled tree-topology power routing has been shown to be critical for minimizing chip area and providing low spatial pattern noise. Imaging artifacts due to timing asymmetry has been quantified, and methods for elimination of the artifacts have been demonstrated. The impact of on-chip bias-generation and drive circuits on the on-chip ADC performance has been shown. New timing and circuit layout techniques has been presented for enabling random noise limited performance of a CMOS imager.
|
 Additional Information
|
Citation:
Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang, Suresh Seshadri, Julie Heynssens, Chris Wrigley,
"CMOS Digital Imager Design from a System-on-a-chip Perspective,"
vlsid,
p. 395,
16th International Conference on VLSI Design,
2003
|
|
