vlsid,ASP-DAC/VLSI Design 2002

Published Articles >> Table of Contents

ASP-DAC/VLSI Design 2002


Message from the General Chair (PDF) p. xv
Message from the Program Chairs (PDF) p. xvii
VLSI Design and ASPDAC Conference Committee (PDF) p. xix
VLSI Design and ASPDAC Technical Program Committee (PDF) p. xxi
VLSI Design Steering Committee (PDF) p. xxiii
ASPDAC Steering Committee (PDF) p. xxiv
VLSI Design 2001 Conference Awards (PDF) p. xxvi
Reviewers (PDF) p. xxvii
Conference History (PDF) p. xxx
Keynote Talks
Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges (PDF) Biswadip Mitra p. 3
LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era (PDF) Kazuo Yano p. 5
Electronic Industry on Fire: How to Survive and Thrive (PDF) Aart J. de Geus p. 6
Digital Watermarking (PDF) Martin F.H. Schuurmans p. 7
Tutorials: Chair: R. A. Parekhji
Functional Verification of System on Chips-Practices, Issues and Challenges (Abstract) Subir K. Roy, Synplicity, Inc S. Ramesh, Indian Institute of Technology Bombay Supratik Chakraborty, Indian Institute of Technology Bombay Tsuneo Nakata, Fujitsu Laboratories Limited, Japan Sreeranga P. Rajan, Fujitsu Laboratories of America, USA p. 11
T2: System-Level Design of Embedded Media Systems (PDF) P. Van der Wolf W. Kruijtzer J. Van Eijndhoven p. 14
T3: Trends and Challenges in VLSI Technology Scaling towards 100nm (PDF) S. Rusu M. Sachdev C. Svensson B. Nauta p. 16
T4: Mathematical Methods in VLSI (PDF) M. V. Atre P. S. Subramanian H. Narayanan p. 18
T5: Electronic Testing for SOC Designers (PDF) V. D. Agrawal M. L. Bushnell p. 20
Specification, Modeling and Design Tools for System-on-Chip (Abstract) Luciano Lavagno, Cadence Berkeley Laboratories Sujit Dey, University of California at San Diego Rajesh Gupta, University of California at Irvine p. 21
T7: MEMS: Technology, Design, CAD and Applications (PDF) R. Lal P. R. Apte K. N. Bhat G. Bose S. Chandra D. K. Sharma p. 24
T8: Logic Design of Asynchronous Circuits (PDF) J. Cortadella A. Yakovlev J. Garside p. 26
Session 1A: Low Power I: Chair: Niraj Jha
Evaluating Run-Time Techniques for Leakage Power Reduction (Abstract) David Duarte, The Pennsylvania State University Yuh-Fang Tsai, The Pennsylvania State University Narayanan Vijaykrishnan, The Pennsylvania State University Mary Jane Irwin, The Pennsylvania State University p. 31
Topological Analysis for Leakage Prediction of Digital Circuits (Abstract) Wenjie Jiang, Intel Corporation Vivek Tiwari, Intel Corporation Erik de la Iglesia, Aplatform Internet Service Amit Sinha, Massachusetts Institute Of Technology p. 39
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment (Abstract) Rahul Kumar, Sasken Communication Technologies Ltd. C.P. Ravikumar, Texas Instruments India Pvt Ltd p. 45
Estimation of Maximum Power-up Current (Abstract) Fei Li, University of Wisconsin-Madison Lei He, University of Wisconsin-Madison Kewal K. Saluja, University of Wisconsin-Madison p. 51
Session 2A: Interconnects and Technology I: Chair: V. Visvanathan
Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method (Abstract) Joong-Ho Kim, Georgia Institute of Technology Erdem Matoglu, Georgia Institute of Technology Jinwoo Choi, Georgia Institute of Technology Madhavan Swaminathan, Georgia Institute of Technology p. 59
Dynamic Noise Analysis with Capacitive and Inductive Coupling (Abstract) Seung Hoon Choi, Purdue University Bipul C. Paul, Purdue University Kaushik Roy, Purdue University p. 65
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models (Abstract) Makoto Nagata, Hiroshima University Youichi Nishimori, Hiroshima University Takashi Morie, Hiroshima University Atsushi Iwata, Hiroshima University Yoshitaka Murasaka, A-R-Tec Corp. p. 71
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis (Abstract) Kanak Agarwal Yu Cao Takashi Sato Dennis Sylvester Chenming Hu p. 77
Session 3A: Synthesis I: Chair: Yusuke Matsunaga
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis (Abstract) Rupesh S. Shelar, University of Minnesota Sachin S. Sapatnekar, University of Minnesota p. 87
Design of Asynchronous Controllers with Delay Insensitive Interface (Abstract) Hiroshi Saito, The Uuniversity of Tokyo Takashi Nanya, The Uuniversity of Tokyo Alex Kondratyev, Cadence Design Systems p. 93
Synthesis of High Performance Low Power Dynamic CMOS Circuits (Abstract) Debasis Samanta, Indian Institute of Technology Kharagpur Ajit Pal, Indian Institute of Technology Kharagpur Nishant Sinha, Carnegie Mellon University p. 99
Improvement of ASIC Design Processes (Abstract) Vineet Sahula C. P. Ravikumar D. Nagchoudhuri p. 105
Session 1B: Low Power II: Chair: A. Raghunathan
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs (Abstract) Haris Lekatsas, NEC USA Joerg Henkel, NEC USA p. 113
Weight-Based Bus-Invert Coding for Low-Power Applications (Abstract) Rung-Bin Lin, Yuan-Ze University Chi-Ming Tsai, Yuan-Ze University p. 121
Software-Only Bus Encoding Techniques for an Embedded System (Abstract) Wei-Chung Cheng, University of Southern California Jian-Lin Liang, University of Southern California Massoud Pedram, University of Southern California p. 126
Interconnect Energy Dissipation in High-Speed ULSI Circuits (Abstract) Payam Heydari, University of California at Irvine Massoud Pedram, University of Southern California p. 132
Session 2B: Interconnects and Technology II: Chair: Anil Gundurao
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification (PDF) N. S. Nagaraj P. Balsara C. Cantrell p. 141
Losses in Multilevel Crossover in VLSI Interconnects (Abstract) P.K. Datta, Indian Institute of Technology, Kharagpur S. Sanyal, Indian Institute of Technology, Kharagpur D. Bhattacharya, Indian Institute of Technology, Kharagpur p. 142
Rational ABCD Modeling of High-Speed Interconnects (Abstract) Qinwei Xu, University of Michigan Pinaki Mazumder, University of Michigan p. 147
Session 3B: Synthesis II: Chair: Anshul Kumar
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization (Abstract) Kuo-Hsing Cheng, Tamkang University Shun-Wen Cheng, Tamkang University p. 155
A New Synthesis of Symmetric Functions (Abstract) Hafizur Rahaman, A. P. C. Roy Polytechnic College Debesh K. Das, Jadavpur University Bhargab B. Bhattacharya, University of Nebraska-Lincoln p. 160
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA (Abstract) Hiroaki Yoshida, University of Tokyo Hiroaki Yamaoka, University of Tokyo Makoto Ikeda, University of Tokyo Kunihiro Asada, University of Tokyo p. 166
Register Transfer Operation Analysis during Data Path Verification (Abstract) D. Sarkar, Indian Institute of Technology at Kharagpur p. 172
Session 1C: Low Power III: Chair: Sujit Dey
A Real Delay Switching Activity Simulator based on Petri net Modeling (Abstract) Ashok K. Murugavel, University of South Florida N. Ranganathan, University of South Florida p. 181
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks (Abstract) Sanjukta Bhanja, University of South Florida N. Ranganathan, University of South Florida p. 187
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits (Abstract) Debasis Samanta, Indian Institute of Technology Kharagpur Ajit Pal, Indian Institute of Technology Kharagpur p. 193
Minimizing Energy Consumption for High-Performance Processing (Abstract) Eric F. Weglarz, University of Wisconsin - Madison Kewal K. Saluja, University of Wisconsin - Madison Mikko H. Lipasti, University of Wisconsin - Madison p. 199
Session 2C: Interconnects and Technology III: Chair: G. S. Visweswaran
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis (Abstract) A.B. Bhattacharyya, Goa University Shrutin Ulman, Goa University p. 207
A Parallel and Accelerated Circuit Simulator with Precise Accuracy (Abstract) Peter M. Lee Shinji Ito Takeaki Hashimoto Tomomasa Touma Junji Sato Goichi Yokomizo p. 213
Timing Yield Calculation Using an Impulse-train Approach (Abstract) Srinath R. Naidu, Eindhoven University of Technology p. 219
Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay (Abstract) H.C. Srinivasaiah, Indian Institute of Science, Bangalore Navakanta Bhat, Indian Institute of Science, Bangalore p. 225
Session 3C: Synthesis III: Chair: P. P. Chakrabarti
Exploring the Number of Register Windows in ASIP Synthesis (Abstract) Vishal P. Bhatt, Synposys India M. Balakrishnan, Indian Institute of Technology Delhi Anshul Kumar, Indian Institute of Technology Delhi p. 233
Architecture Implementation Using the Machine Description Language LISA (Abstract) Oliver Schliebusch, University of Technology Aachen Andreas Hoffmann, University of Technology Aachen Achim Nohl, University of Technology Aachen Gunnar Braun, University of Technology Aachen Heinrich Meyr, University of Technology Aachen p. 239
A Framework for Design Space Exploration of Parameterized VLSI Systems (Abstract) Giuseppe Ascia Vincenzo Catania Maurizi Palesi, Università di Catania p. 245
An Evolutionary Scheme for Cosynthesis of Real-Time Systems (Abstract) S. Chakraverty, Netaji Subhas Institute of Technology C.P. Ravikumar, Texas Instrucments, India D.Roy Choudhuri, Delhi College of Engineering p. 251
Panel
Entrepreneurship in VLSI: The Next Frontier Coordinator: M. Chandrasekaran Panelists: R. Mody R. Pai A. Shelat D. Sharma
Session 4A: Low Power IV: Chair: R. Gupta
Battery-Driven System Design: A New Frontier in Low Power Design (Abstract) Kanishka Lahiri, University of California at San Diego Sujit Dey, University of California at San Diego Debashis Panigrahi, University of California at San Diego Anand Raghunathan, NEC USA p. 261
A Power Minimization Technique for Arithmetic Circuits by Cell Selection (Abstract) Masanori Muroyama, Kyushu University Akihiko Hyodo, Kyushu University Hiroto Yasuura, Kyushu University Tohru Ishihara, University of Tokyo p. 268
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip (Abstract) Yunsi Fei, Princeton University Niraj K. Jha, Princeton University p. 274
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories (Abstract) Tohru Ishihara, University of Tokyo Kunihiro Asada, University of Tokyo p. 282
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories (Abstract) V. Delaluz, Pennsylvania State University M. Kandemir, Pennsylvania State University N. Vijaykrishnan, Pennsylvania State University M. J. Irwin, Pennsylvania State University A. Sivasubramaniam, Pennsylvania State University I. Kolcu, Pennsylvania State University p. 288
Session 5A: Interconnects and Technology IV: Chair: Nagaraj Subramanyam
Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI (PDF) S. Natarajan A. Marshall p. 297
Transistor Flaring in Deep Submicron-Design Considerations (Abstract) Vipul Singhal C.B. Keshav K.G. Surnanth P. .R. Suresh p. 299
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI (Abstract) Shuzhou Fang, Tsinghua Uuniversity Zeyi Wang, Tsinghua Uuniversity Xianlong Hong, Tsinghua Uuniversity p. 305
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods (Abstract) Q. Su, Purdue University V. Balakrishnan, Purdue University C-K. Koh, Purdue University p. 311
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches (Abstract) Maryam Shojaei Baghini, MicroElectronics Group Madhav P. Desai, MicroElectronics Group p. 317
Session 6A: Synthesis IV: Chair: P. van der Wolf
Embedded Tutorial: General Architectural Concepts for IP Core Re-Use (PDF) P. Klapproth p. 325
Framework for Synthesis of Virtual Pipelines (Abstract) Srinivasan Dasasathyan, University of Cincinnati Rajesh Radhakrishnan, University of Cincinnati Ranga Vemuri, University of Cincinnati p. 326
Automatic Model Refinement for Fast Architecture Exploration (Abstract) Junyu Peng, University of California at Irvine Samar Abdi, University of California at Irvine Daniel Gajski, University of California at Irvine p. 332
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors (Abstract) Francisco Barat Murali Jayapala Pieter Op de Beeck Geert Deconinck K.U. Leuven p. 338
Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs (Abstract) Li Shang, Princeton University Niraj K. Jha, Princeton University p. 345
Session 4B: Analog Design: Chair: Makato Nagata
A Design of Analog C-Matrix Circuits used for Signal/Data Processing (Abstract) Takayuki Sugawara, Hokkaido University Yoshikazu Miyanaga, Hokkaido University Norinobu Yoshida, Hokkaido University p. 355
A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment (Abstract) Debapriya Sahu, Texas Instruments, Bangalore, India p. 360
Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach (Abstract) Biranchinath Sahu, Georgia Institute of Technology Aloke K. Dutta, Indian Institute of Technology p. 366
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing (Abstract) Jens Lienig, Robert Bosch GmbH Goeran Jerke, Robert Bosch GmbH Thorsten Adler, sci-worx GmbH p. 372
Session 5B: Layout I: Chair: Narendra Shenoy
Buffered Routing Tree Construction Under Buffer Placement Blockages (Abstract) Wei Chen, University of Southern California Massoud Pedram, University of Southern California Premal Buch, Magma Design Automation p. 381
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks (Abstract) Yuchun Ma, Tsinghua University Xianlong Hong, Tsinghua University Sheqin Dong, Tsinghua University Yici Cai, Tsinghua University Chung-Kuan Cheng, University of California at San Diego Jun Gu, University of HongKong p. 387
An Adaptive Interconnect-Length Driven Placer (Abstract) Chi-Ming Tsai, Yuan-Ze University Kun-Tien Kuo, Yuan-Ze University Chyi-Hui Hong, Yuan-Ze University Rung-Bin Lin, Yuan-Ze University p. 393
Net Clustering Based Macrocell Placement (Abstract) Stelian Alupoaei, University of South Florida Srinivas Katkoori, University of South Florida p. 399
Session 6B: Synthesis and Verification: Chair: S. Ramesh
High-Level Synthesis with SIMD Units (Abstract) Vijay Raghunathan, University of California at Los Angeles Mani B. Srivastava, University of California at Los Angeles Milos D. Ercegovac, University of California at Los Angeles Anand Raghunathan, NEC-USA p. 407
A Heuristic for Clock Selection in High-Level Synthesis (Abstract) J. Ramanujam, Louisiana State University Sandeep Deshpande, Louisiana State University Jinpyo Hong, Louisiana State University Mahmut Kandemir, The Pennsylvania State University p. 414
Design for Verification at the Register Transfer Level (Abstract) Indradeep Ghosh, Fujitsu Labs. of America, Inc. Krishna Sekar, University of California at San Diego Vamsi Boppana, Zenasis Tech. Inc. p. 420
Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design (Abstract) G. Nicolescu, TIMA Laboratory S. Martinez, TIMA Laboratory L. Kriaa, TIMA Laboratory W. Youssef, TIMA Laboratory S. Yoo, TIMA Laboratory B. Charlot, TIMA Laboratory A. Jerraya, TIMA Laboratory p. 426
Session 4C: VLSI Architecture I: Chair: N. Ranganathan
VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme (Abstract) Kavish Seth, Indian Institute Technology at Madras S. Srinivasan, Indian Institute Technology at Madras p. 435
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation (Abstract) Hak-soo Yu, The University of Texas at Austin Jacob A. Abraham, The University of Texas at Austin p. 441
Architecture and Design of a High Performance SRAM for SoC Design (Abstract) Shobha Singh, STMicroelectronics Shamsi Azmi, STMicroelectronics Nutan Aarawal, STMicroelectronics Penaka Phani, STMicroelectronics Ansuman Rout, STMicroelectronics p. 447
VLSI Architecture for a Flexible Motion Estimation with Parameters (Abstract) Jinku Choi, Waseda University Masao Yanagisawa, Waseda University Tatsuo Ohtsuki, Waseda University Nozomu Togawa, The University of Kitakyushu p. 452
Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language (Abstract) Prabhat Mishra, University of California at Irvine Ashok Halambi, University of California at Irvine Peter Grun, University of California at Irvine Nikil Dutt, University of California at Irvine Alex Nicolau, University of California at Irvine Hiroyuki Tomiyama, ISIT p. 458
Session 5C: Layout II: Chair: Susmita Sur-Kolay
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts (Abstract) Yukiko Kubo, The University of Kitakyushu Shigetoshi Nakatake, The University of Kitakyushu Yoji Kajitani, The University of Kitakyushu Masahiro Kawakita, Toshiba Corp. p. 467
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing (Abstract) Jingyu Xu, Tsinghua University Xianlong Hong, Tsinghua University Tong Jing, Tsinghua University Yici Cai, Tsinghua University Jun Gu, Hong Kong University of Science & Technology p. 473

	Advanced Search
CS Search Google Search