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ASP-DAC/VLSI Design 2002   p. 535
A New Divide and Conquer Method for Achieving High Speed Division in Hardware
Murali Mohan, Indian Institute Of Technology
Rohini Krishnan, Indian Institute Of Technology
Anshul Kumar, Indian Institute Of Technology
M. Balakrishnan, Indian Institute Of Technology

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994974
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Abstract
In this paper, we present a new method of performing Division in Hardware and explore different ways of implementing it. This method involves computing a preliminary estimate of the quotient by splitting the Dividend, performing division of each of the parts in parallel and merging them. The estimate is refined iteratively to get the final quotient. This method is significantly fast since it carries out parallel operations to compute the preliminary quotient and makes use of a fast multiplier to refine the result. It is possible to pipeline the execution of the unit yielding further increase in throughput. Speed estimates show that this method yields a much higher throughput than other fast methods, while area and latency are comparable
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Index Terms- Pipelineability,Latency,Throughput,Rounding,Radix,SRT,Carry Save Adders,Carry Propagate Adders Citation:  Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan, "A New Divide and Conquer Method for Achieving High Speed Division in Hardware," vlsid, p. 535,  ASP-DAC/VLSI Design 2002,  2002