| Abstract |
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This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a technique, based on adding an operation assignment phase to software pipelining, that performs reconfigurable instruction generation and instruction scheduling on a combined algorithm. Although typical compilers for reconfigurable processors perform these steps separately, results show that the combination enables a successful usage of the reconfigurable resources. The assignment algorithm is the key for using software pipelining on the reconfigurable processor.The technique presented is also able to exploit spatial computation inside the reconfigurable functional unit by which the output of a processing element is directly connected to the input of another processing element without the need of an intermediate register. Results show that it is possible to reduce the cycle count by using this spatial computation.
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 Additional Information
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Index Terms- reconfigurable processor, code generation, coarse grained logic, software pipelining, vliw, spatial computation
Citation:
Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck, K.U. Leuven,
"Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors,"
vlsid,
p. 338,
ASP-DAC/VLSI Design 2002,
2002
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