A Power Minimization Technique for Arithmetic Circuits by Cell Selection

1bit full adders and counters are usually used as basic cells in the arithmetic circuits. Characteristics of these components have strong impact on power, delay, and area of the arithmetic circuits. In this paper we propose a design method for low power arithmetic circuits, which the designer selects basic cells from a set of circuits with different structures(symmetrical one and asymmetrical one) by the method and the mothod optimizes connections to the terminals of the basic cells. Experimental results demonstrate 32.1% power reduction of a parallel multiplier designed by the proposed technique.