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25th IEEE International Real-Time Systems Symposium (RTSS'04)   pp. 92-103
Modeling Out-of-Order Processors for Software Timing Analysis
Xianfeng Li, National University of Singapore
Abhik Roychoudhury, National University of Singapore
Tulika Mitra, National University of Singapore

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/REAL.2004.33
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Abstract
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typically model the timing effects of microarchitectural features in modern processors (such as the pipeline, caches, branch prediction, etc.) to obtain safe but tight estimates. In this paper, we model out-of-order processor pipelines for WCET analysis. This analysis is, in general, difficult even for a basic block (a sequence of instructions with single-entry and single-exit points) if some of the instructions have variable latencies. This is because the WCET of a basic block on out-of-order pipelines cannot be obtained by assuming maximum latencies of the individual instructions. Our timing estimation technique for a basic block is inspired by an existing performance analysis technique for tasks with data dependences and resource contentions in real-time distributed systems. We extend our analysis by modeling the interaction among consecutive basic blocks as well as the effect of instruction cache. Finally, we employ Integer Linear Programming (ILP) to compute the WCET of an entire program. The accuracy of our analysis is demonstrated via tight estimates obtained for several benchmarks.
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Citation:  Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, "Modeling Out-of-Order Processors for Software Timing Analysis," rtss, pp. 92-103,  25th IEEE International Real-Time Systems Symposium (RTSS'04),  2004