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24th IEEE International Real-Time Systems Symposium (RTSS'03)   p. 275
Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores
Marcio Buss, University of California, Irvine
Tony Givargis, University of California, Irvine
Nikil Dutt, University of California, Irvine

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/REAL.2003.1253274
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Abstract
Portable and battery operated devices pose a unique design challenge in terms of performance requirements, low power constraints, and shrot design cycles. Embedded soft cores, on the other hand, provide functional flexibility and guarantee rapid design and thus are gaining popularity in designing such portable and battery operated devices. To address the low power needs, dynamic voltage scaled (DVS) processors provide a new tradeoff dimension to the designer. This work proposes an application-specific design space exploration framework for selecting energy-efficient operating points in an embedded soft core. Specifically, we address the problem of selecting an appropriate number of operating voltage/frequency points and the distribution of these points along the valid voltage span of a processor, given the application that is to be executed on the processor. Furthermore, we provide a static intra-task scheduling technique that reduces energy consumption (4-20% in our experiments) even when the worst-case application execution time does not leave any slack for effective voltage scaling. We have experimentally verified our techniques on a large set of embedded benchmarks selected from MiBench, PowerStone and MediaBench.
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Citation:  Marcio Buss, Tony Givargis, Nikil Dutt, "Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores," rtss, p. 275,  24th IEEE International Real-Time Systems Symposium (RTSS'03),  2003