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24th IEEE International Real-Time Systems Symposium (RTSS'03)   p. 265
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
Jan Madsen, Technical University of Denmark
Shankar Mahadevan, Technical University of Denmark
Kashif Virk, Technical University of Denmark
Mercury Gonzalez, Technical University of Denmark

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/REAL.2003.1253273
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Abstract
With the increasing number of transistors available on a single chip, the System-on-Chip (SoC) paradigm has evolved to exploit its full potential. As many processors can be accommodated on a single chip, this paradigm has forced a communication-centric, as opposed to a computation-centric, design view. Thus, the choice, management and modeling of the SoC interconnect is essential for an accurate evaluation and optimization of the global performance of a system. Recently, the notion of Network-on-Chip (NoC) has been introduced as a way to extend the classical bus-based interconnection, which is still the dominant interconnect structure for SoC's, into a dedicated, segmented and, possibly, packet-switched network fabric [2]. In this paper, we present a NoC model which, together with a multiprocessor real-time operating system (RTOS) model, allows us to model and analyze the behavior of a complex system that has a real-time application running on a multiprocessor platform. We demonstrate the potential of our model by simulating and analyzing a small multiprocessor system connected through different NoC topologies, and discus how the simulation model may be used during the design-space exploration phase.
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Citation:  Jan Madsen, Shankar Mahadevan, Kashif Virk, Mercury Gonzalez, "Network-on-Chip Modeling for System-Level Multiprocessor Simulation," rtss, p. 265,  24th IEEE International Real-Time Systems Symposium (RTSS'03),  2003