| Abstract |
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In this paper we present a technique for Worst-Case Execution Time (WCET) analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipeline modeling. Our technique handle CPUs that execute multiple shorter instructions in parallel with long-running instructions. The results of other machine analyses, like cache analysis, can be used in our pipeline analysis. Also, results from high-level program flow analysis can be used to tighten the execution time predictions. Our primary target is embedded real-time systems, and since processor simulators are standard equipment for embedded development work, our tool will be easy to port to relevant target processors.
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 Additional Information
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Index Terms- WCET, pipeline analysis, hard real-time, embedded systems
Citation:
Jakob Engblom, Andreas Ermedahl,
"Pipeline Timing Analysis Using a Trace-Driven Simulator,"
rtcsa,
p. 88,
Sixth International Conference on Real-Time Computing Systems and Applications (RTCSA'99),
1999
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