Abstract
A high performance IPC (Inter-Processor Communication) controller for the multiprocessors of an ATM switching system is proposed in this paper. This IPC controller accommodates the ATM cell assembly and reassembly functions and allows high-speed interprocessor data transfer via ATM switch. The IPC controller structure consists of the segmentation part and the reassembly part for processing AAL type 5. The IPC protocol is implemented sliding window method. The real message ratio and the LPC controller performance is computed according to user packet size. The real message ratio is increased as the user packet size increases because of header overhead. And the maximum real message ratio is about 0.8 in maximum user packet size 496 bytes. The throughput is optimal at packet size 80.