Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems

A. Mukherjee; N. Motgi; J. Becker; A. Friebe; C. Habermann; M. Glesner

doi:10.1109/IWRSP.2001.933839

Rapid System Prototyping, IEEE International Workshop on

Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems

Year: 2001, Pages: 0058

DOI Bookmark: 10.1109/IWRSP.2001.933839

Authors

A. Mukherjee, University of Central Florida
N. Motgi, University of Central Florida
J. Becker, Institute of Microelectronic Systems, Darmstadt University of Technology
A. Friebe, Institute of Microelectronic Systems, Darmstadt University of Technology
C. Habermann, Institute of Microelectronic Systems, Darmstadt University of Technology
M. Glesner, Institute of Microelectronic Systems, Darmstadt University of Technology

Abstract

Abstract: Due to high bandwidth requirements up to 2 Mbits/sec in third generation mobile communication systems, efficient data compression approaches are necessary to reduce communication and storage costs. Recent VLSI technologies status promises complete System-on-Chip (SoC) solutions for both mobile and network based communication systems, including new compression algorithms based on Burrows-Wheeler transform (BWT). The most complex task of the BWT algorithm is its lexicographic sorting of n cyclic rotations of a given string of n characters. The paper discusses the feasibility and VLSI implementation of this scalable BWT architecture in simulating and prototyping its systolic highly utilized hardware structure with Virtex FPGAs.

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