Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features

10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04) pp. 49-54
Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features
Amir Rajabzadeh, Sharif University of Technology
Mirzad Mohandespour, Sharif University of Technology
Ghassem Miremadi, Sharif University of Technology

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.2004.1276552
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Abstract
Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and realtime systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium® processor. The results show that the error detection coverage varies between to 90.92% and 98.41%, for different workloads.
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Citation: Amir Rajabzadeh, Mirzad Mohandespour, Ghassem Miremadi, "Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features," prdc, pp. 49-54, 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), 2004

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