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Published Articles >> Table of Contents >> Abstract
12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03)
p. 125
Spill Code Minimization by Spill Code Motion
Akira Koseki, IBM Tokyo Research Laboratory
Hideaki Komatsu, IBM Tokyo Research Laboratory
Toshio Nakatani, IBM Tokyo Research Laboratory
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACT.2003.1238009
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| Abstract |
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This paper aims at minimizing the spill costs. Spill cost minimization heuristics that have been researched sometimes work in unexpected ways due to the lack of precise knowledge of registers availability, which can be obtained only after register allocation is all finished. Different from previous techniques, our approach, called spill code motion, tries to eliminate redundancy among spill code. This works as a variation of commonly used code motion techniques. After Chaitin-style graph coloring with naïve live range splitting, spill-in instructions are first hoisted as long as registers are available and until they reach spillout instructions. Unnecessarily hoisted spill-in instructions are then sunk. The experimental results show our approach yields up to a 10% performance increase compared to the latest spill code minimization technique in the case of using small number of registers.
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Citation:
Akira Koseki, Hideaki Komatsu, Toshio Nakatani,
"Spill Code Minimization by Spill Code Motion,"
pact,
p. 125,
12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03),
2003
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