Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)

T. Devoivre; M. Lunenborg; C. Julien; J-P. Carrere; P. Ferreira; W. J. Toren; A. VandeGoor; P. Gayet; T. Berger; O. Hinsinger; P. Vannier; Y. Trouiller; Y. Rody; P-J. Goirand; R. Palla; I. Thomas; F. Guyader; D. Roy; B. Borot; N. Planes; S. Naudet; F. Pico; D. Duca; F. Lalanne; D. Heslinga; M. Haond

doi:10.1109/MTDT.2002.1029778

Records of the 2002 IEEE International Workshop on Memory Technology, Design and Testing

Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)

Year: 2002, Pages: 157

DOI Bookmark: 10.1109/MTDT.2002.1029778

Authors

T. Devoivre, STMicroelectronics
M. Lunenborg, PHILIPS Semiconductors
C. Julien, STMicroelectronics
J-P. Carrere, STMicroelectronics
P. Ferreira, STMicroelectronics
W. J. Toren, PHILIPS Semiconductors
A. VandeGoor, PHILIPS Semiconductors
P. Gayet, STMicroelectronics
T. Berger, STMicroelectronics
O. Hinsinger, STMicroelectronics
P. Vannier, STMicroelectronics
Y. Trouiller, LETI
Y. Rody, PHILIPS Semiconductors
P-J. Goirand, STMicroelectronics
R. Palla, STMicroelectronics
I. Thomas, STMicroelectronics
F. Guyader, STMicroelectronics
D. Roy, STMicroelectronics
B. Borot, STMicroelectronics
N. Planes, STMicroelectronics
S. Naudet, STMicroelectronics
F. Pico, STMicroelectronics
D. Duca, STMicroelectronics
F. Lalanne, STMicroelectronics
D. Heslinga, PHILIPS Semiconductors
M. Haond, STMicroelectronics

Abstract

This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16 Å EOT-70nm transistors (standard process) or 21 -90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1Mbit SRAM instances, based on a highly manufacturable 6T 1.36?m? memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.

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Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)

Authors

Abstract

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