Abstract
The objective of this paper is to present an Automated Design methodology for EEPROM cell (ADE). This method focuses on EEPROM cell geometry automatic generation for a targeted program window including constraints like robustness to process variation, program high voltage and electric field minimization. The method is based on a mathematical model generated with a "Design Of Simulation" (DOS) technique. The DOS technique takes as input, simulations results of a floating gate transistor for different given geometries and program high voltages. It produces, as output, polynomial equations of the threshold voltages and maximal electric field in function of the geometric parameters and of the program high voltage. Using those equations, the design process is realized in two steps. In a first step, a set of cells (geometry and high voltage) meeting a targeted threshold voltages window is generated. From this set of cells, the optimal cell is selected under robustness, high voltage and electric field minimization criteria.