Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme

Kyung-Saeng Kim; KwangMyoung Rho; Kwyro Lee

doi:10.1109/MTDT.2001.945222

Memory Technology, Design and Testin, IEEE International Workshop on

Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme

Year: 2001, Pages: 0009

DOI Bookmark: 10.1109/MTDT.2001.945222

Authors

Kyung-Saeng Kim, Korea Advanced Institute of Science and Technology (KAIST)
KwangMyoung Rho, Korea Advanced Institute of Science and Technology (KAIST)
Kwyro Lee, Korea Advanced Institute of Science and Technology (KAIST)

Abstract

Abstract: An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line to bit-line contact scheme in the orthogonal RAM cell array architecture leads to asymmetric bit-line sensing scheme and (i, 2i) bit-line transposing scheme, and results in fast response time of the sense amplifier and low power dissipation for restoring.

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