Teaching Trade-offs in System-level Design Methodologies

K. Sakiyama; P. Schaumont; D. Hwang; I. Verbauwhede

doi:10.1109/MSE.2003.1205256

Microelectronic Systems Education Conference

Teaching Trade-offs in System-level Design Methodologies

Year: 2003, Pages: 62

DOI Bookmark: 10.1109/MSE.2003.1205256

Authors

K. Sakiyama, University of California, Los Angeles
P. Schaumont, University of California, Los Angeles
D. Hwang, University of California, Los Angeles
I. Verbauwhede, University of California, Los Angeles

Abstract

This paper summarizes two graduate-level class projects in EE201A/EE298 (VLSI Architectures and Design Methods) at the University of California, Los Angeles (UCLA). The purpose of the class is to explore the impact of system-level optimization for various target platforms using EDA.

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Teaching Trade-offs in System-level Design Methodologies

Authors

Abstract

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