| Abstract |
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Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.
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 Additional Information
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Citation:
Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford,
"Teaching Pipelining and Concurrency using Hardware Description Languages,"
mse,
p. 55,
IEEE International Conference on Microelectronic Systems Education,
1999
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