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Published Articles >> Table of Contents >> Abstract
First ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE’03)
p. 65
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions
Sudarshan K. Srinivasan, Georgia Institute of Technology, Atlanta
Miroslav N. Velev, Georgia Institute of Technology, Atlanta
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MEMCOD.2003.1210090
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| Abstract |
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We present the formal verification of an Intel Xscale processor model. The Xscale is a superpipelined RISC processor with 7-stage integer, 8-stage memory, and variable-latency multiply-and-accumulate execution pipelines. The processor uses scoreboarding to track data dependencies, and implements both precise and imprecise exceptions. Such set of features had not been modeled, and formally verified previously. The formal verification was done with an automatic toll flow that consists of the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker.
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Citation:
Sudarshan K. Srinivasan, Miroslav N. Velev,
"Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions,"
memocode,
p. 65,
First ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE’03),
2003
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