A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC

Samiran Halder; Swapna Banerjee; Arindrajit Ghosh; Ravi sankar Prasad; Anirban Chatterjee; Sanjoy Kumar Dey

doi:10.1109/ICVD.2005.6

VLSI Design, International Conference on

A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC

Year: 2005, Pages: 319-322

DOI Bookmark: 10.1109/ICVD.2005.6

Authors

Samiran Halder, IHP- Germany
Swapna Banerjee, Indian Institute of Technology-Kharagpur
Arindrajit Ghosh, Indian Institute of Technology-Kharagpur
Ravi sankar Prasad, Indian Institute of Technology-Kharagpur
Anirban Chatterjee, Qualcorelogic Ltd Habsiduda
Sanjoy Kumar Dey, Indian Institute of Technology-Kharagpur

Abstract

This Paper presents a 10 bits 80 MSPS 2.5 V digital-to-analog converter (DAC) using 0.25 micrometer double poly four metal CMOS technology for mixed-signal applications. A segmented current steering architecture is used for this DAC. This architecture gives the most optimized results in terms of speed, resolution, area and power. The DAC can operate at a frequency of 80MHz and above. Total power dissipation is 27.6525 mW with 2.5 V power supply. It achieves differential nonlinearity and integral nonlinearity of ?0.55 LSB and ?0.4 LSB. It occupies an area of 0.185 mm².

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A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC

Authors

Abstract

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