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Published Articles >> Table of Contents >> Abstract
International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2
p. 546
Power-Analysis Attack on an ASIC AES implementation
Siddika Berna Örs, Katholieke Universiteit Leuven, Belgium
Frank Gürkaynak, Integrated Systems Laboratory ETH Zentrum, Switzerland
Elisabeth Oswald, Institute for Applied Information Processing and Communications (IAIK), Austria; A-SIT, Technologiebeobachtung, Austria
Bart Preneel, Katholieke Universiteit Leuven, Belgium
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITCC.2004.1286711
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| Abstract |
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The AES (Advanced Encryption Standard) is a new block
cipher standard published by the US government in November
2001. As a consequence, there is a growing interest
in efficient implementations of the AES. For many applications,
these implementations need to be resistant against
side channel attacks, that is, it should not be too easy to
extract secret information from physical measurements on
the device. This article presents the first results on the feasibility
of power analysis attack against an AES hardware
implementation. Our attack is targeted against an ASIC implementation
of the AES developed by the ETH Zurich. We
show how to build a reliable measurement setup and how to
improve the correlation coefficients, i.e., the signal to noise
ratio for our measurements. Our approach is also the first
step to link a behavior HDL simulator generated simulated
power measurements to real power measurements.
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 Additional Information
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Index Terms- AES, power analysis attack
Citation:
Siddika Berna Örs, Frank Gürkaynak, Elisabeth Oswald, Bart Preneel,
"Power-Analysis Attack on an ASIC AES implementation,"
itcc,
p. 546,
International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2,
2004
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