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International Test Conference 2003 (ITC'03)   p. 358
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
Kevin Melocco, Cadence Design Systems - Test Design Automation - Endicott, NY
Hina Arora, Cadence Design Systems - Test Design Automation - Endicott, NY
Paul Setlak, Cadence Design Systems - Test Design Automation - Endicott, NY
Gary Kunselman, IBM Microelectronics - DFTS Development and Methodology - Burlington, VT
Shazia Mardhani, Sun Microsystems - High End Server Engineering - Burlington, MA

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270858
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Abstract
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise list of errors as well as good debug and diagnostic information using graphical analysis. The paper provides a review of the methods used to perform the logic verification. We introduce an efficient technique for verifying the correspondence of chip I/O with the boundary scan register and for verifying large scan registers. The tool is independent of how the test logic is instantiated. The tool requires only the design netlist, cell library definition, and its BSDL [2] identifying what 1149.1 test logic has been implemented. Results on current large ASIC designs is included [10].
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Citation:  Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunselman, Shazia Mardhani, "A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic," itc, p. 358,  International Test Conference 2003 (ITC'03),  2003