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Published Articles >> Table of Contents >> Abstract
International Test Conference 2003 (ITC'03)
p. 39
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories
Derek Wright, University of Waterloo, Canada
Manoj Sachdev, University of Waterloo, Canada
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.2003.1270823
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| Abstract |
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Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this paper, we carried out a transistor-level fault analysis and devise a search path test algorithm. The proposed algorithm is of the order (nl / log2n) compared to the brute-force algorithm of complexity (nl). For the analyzed CAM, the search path test complexity is reduced by 30x.
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 Additional Information
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Citation:
Derek Wright, Manoj Sachdev,
"Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memories,"
itc,
p. 39,
International Test Conference 2003 (ITC'03),
2003
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