A New Test Generation Approach for Embedded Analogue Cores in SoC

M. Stancic; L. Fang; M. H. H. Weusthof; R. M. W. Tijink; H. G. Kerkhoff

doi:10.1109/TEST.2002.1041840

Proceedings. International Test Conference

A New Test Generation Approach for Embedded Analogue Cores in SoC

Year: 2002, Pages: 861

DOI Bookmark: 10.1109/TEST.2002.1041840

Authors

M. Stancic, University of Twente
L. Fang, University of Twente
M. H. H. Weusthof, University of Twente
R. M. W. Tijink, University of Twente
H. G. Kerkhoff, University of Twente

Abstract

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multi-frequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DfT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

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A New Test Generation Approach for Embedded Analogue Cores in SoC

Authors

Abstract

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