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IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)   p. 246
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
Shalini Ghosh, University of Texas, Austin
Sugato Basu, University of Texas, Austin
Nur A. Touba, University of Texas, Austin

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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183485
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Abstract
This paper describes a echnique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random ordering of the scan cells. For a given test set, our proposed greedy algorithm finds the (locally) optimal scan cell ordering for a given value of \lambda, which is a rade-off parameter hat can be used by he designer to specify the relative importance of area overhead minimization and power minimization. The strength of our algorithm lies in the fact that we use a novel dynamic minimum transition fill (MT-fill) technique to fill the unspecified bits in the test vector. Experiments performed on the ISCAS-89 benchmark suite show a reduction in power (70%for s13207, \lambda = 500) as well as a reduction in layout area (6.72%for s13207, \lambda = 500).
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Citation:  Shalini Ghosh, Sugato Basu, Nur A. Touba, "Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering," isvlsi, p. 246,  IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03),  2003