|
Published Articles >> Table of Contents >> Abstract
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
p. 244
Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test
Bassam Shaer, Department of Electrical & Computer Engineering, UMD
Kailash Aurangabadkar, Department of Computer Science, UMD
Nitin Agarwal, Department of Computer Science, UMD
Full Article Text:
 
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183484
Send link to a friend
| Abstract |
|
In this study, we present an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The partitioning algorithm is based on the primary input cone and fanout value of each node in the circuit. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimenta results are presented to demonstrate the effectiveness of our work.
|
 Additional Information
|
Citation:
Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal,
"Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test,"
isvlsi,
p. 244,
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03),
2003
|
|
