| Abstract |
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Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a business for many years, only recently systematic approaches based on EDA technology are starting to emerge in the marketplace. This paper gives an introduction to IP creation, IP conversion and the necessary infrastructure. We address the technical challenges and show that a strict quality based design methodology is the cornerstone to IP reuse. The paper ends with a brief overview of the current marketplace and an outlook of where the industry may go.
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 Additional Information
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Citation:
Warren Savage, John Chilton, Raul Camposano,
"IP Reuse in the System on a Chip Era,"
isss,
p. 2,
13th International Symposium on System Synthesis (ISSS'00),
2000
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