Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels

Related Articles

• Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode
  2007 20th International Conference on VLSI Design
• Novel Control of DFIG with ESD to Improve LVRT Capability and to Perform Voltage Support during Grid Faults
  2017 IEEE International Conference on Energy Internet (ICEI)
• ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process
  Quality Electronic Design, International Symposium on
• Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs
  2007 20th International Conference on VLSI Design
• Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan
  Proceedings 21st International Conference on Computer Design
• Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits
  ISQED 2003: 4th International Symposium on Quality Electronic Design
• A CMOS Temperature Sensor Using Cascoded PNP Transistors
  Innovations in Bio-inspired Computing and Applications, International Conference on
• High-voltage driving circuit with on-chip ESD protection in CMOS technology
  2017 International Conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS)
• Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• Design of High-Reliability LDO regulator with SCR based ESD Protection circuit using dual buffer structure for low-voltage applications
  2022 6th European Conference on Electrical Engineering & Computer Science (ELECS)