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Published Articles >> Table of Contents >> Abstract
5th International Symposium on Quality Electronic Design (ISQED'04)
pp. 131-136
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids
Woo Hyung Lee, University Michigan
Sanjay Pant, University Michigan
David Blaauw, University Michigan
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283663
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| Abstract |
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Power supply integrity has become a critical concern in modern chip design. To date, analysis of so-called LdI/dt drop in supply networks has mostly focused inductance of the package, which is the predominant factor in inductive voltage drop. However, with increased clock frequencies and power supply demands, on-chip inductance has become a significant factor in the total LdI/dt drop. In this paper, we analyze the impact of on-chip inductance on power supply integrity and propose methods that significantly reduce the voltage drop caused by on-chip inductance. We develop a detailed model of a flip-chip supply network based on an industrial design. The model includes an accurate package model, a PEEC-based model of the on-chip supply interconnects and both intrinsic and explicit on-chip decoupling capacitance. We show that on-chip inductance can account for up to 30% of the total voltage drop in the Giga Hertz processor domain and propose two new on-chip power supply topologies that reduce the on-chip LdI/dt drop by around 70%.
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Citation:
Woo Hyung Lee, Sanjay Pant, David Blaauw,
"Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids,"
isqed,
pp. 131-136,
5th International Symposium on Quality Electronic Design (ISQED'04),
2004
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