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Published Articles >> Table of Contents >> Abstract
5th International Symposium on Quality Electronic Design (ISQED'04)
pp. 98-103
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan
Dongku Kang, Purdue University
Mark C. Johnson, Purdue University
Kaushik Roy, Purdue University
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2004.1283657
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| Abstract |
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In this paper, we propose a simultaneous scheduling and allocation algorithm for voltage-partitioned multiple-Vdddesign. By considering voltage partition during scheduling and allocation, we may place the resources of same voltage in one partition, thereby reducing additional power meshes. Also, the partitioned design reduces the energy dissipation of level converters by reducing cutsize between different-voltage partitions. The proposed algorithm starts from a random solution. Then, it performs scheduling and allocation simultaneously while trying to satisfy both resource and time constraints. By gradually changing the schedule and allocation, the algorithm effectively explores solution spaces to achieve low-power and better partitioning in terms of the supply voltages. Relative to the minimum single voltage design, 36% of energy saving was achieved. Also, improvements for interconnect, level-conversion energy, and voltage clusters were observed.
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 Additional Information
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Citation:
Dongku Kang, Mark C. Johnson, Kaushik Roy,
"Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan,"
isqed,
pp. 98-103,
5th International Symposium on Quality Electronic Design (ISQED'04),
2004
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