Abstract
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit Carry Look Ahead adder (CLA) is designed and simulated using 0.25um CMOS technology to demonstrate 32.7% faster speed than the conventional clocking scheme and 19.4% transistor counter reduction.