Abstract
The development of a new digital communication system has the twofold goal to achieve all traditional requirements from the end user prospective and to offer a huge potential of additional services compared with existing analog systems. The extremely demanding time frame for the introduction of such a system requires a development approach reducing the design risk to a minimum especially for the end user receivers. As integral parts of the terminal the digital baseband processor is one of the most challenging receiver components in terms of development and validation effort. The complexity of the ASIC design with initially estimated 500,000 to 1,000,000 gate equivalents has driven the deployment of a real-time prototyping system. To assure real-time and identical functionality on both FPGA prototype and ASIC behavioral synthesis was used for timing-critical and computationally intensive building blocks. The design and validation methodology was successfully implemented. The ASIC will be introduced in the first generation of mobile radio receivers for digital audio broadcasting in the United States.