ATPG for Path Delay Faults without Path Enumeration

We present a new ATPG methodology for detecting path delay faults in combinational circuits. The proposed approach is non-enumerative and generates a small number of test patterns with high fault coverage. A new ATPG framework for path delay faults is introduced; it collapses the two phases (path sensitization and line justification) of traditional ATPGs into one. The proposed framework utilizes both structural and functional techniques. A BDD-based implementation and experimentation with the ISCAS'85 benchmarks shows that the proposed method outperforms all ATPG methods that bound the test set. The results also show that the approach is comparable to existing ATPG methods that do not bound the test set.