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Published Articles >> Table of Contents >> Abstract
First International Symposium on Quality of Electronic Design
p. 145
Full Chip Thermal Simulation
Zhiping Yu, Stanford University and Hewlett Packard Co.
Dan Yergeau, Stanford University
Robert W. Dutton, Stanford University
Sam Nakagawa, Hewlett Packard Co.
Norman Chang, Hewlett Packard Co.
Shen Lin, Hewlett Packard Co.
Weize Xie, Hewlett Packard Co.
Full Article Text:
  
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2000.838867
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| Abstract |
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A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured to the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical simulation separately on individual functional units. The thermal diffusion equation is then solved based on the actual structure of the chip including substrate and interconnect/insulating layers. Different thermal conductivity can be specified for each material layer. The effect of package on chip temperature distribution is modeled using thermally resistive layers as boundary between the simulated structure and surrounding environment. Proper adjustment of the boundary thermal resistance results in the correct range of simulated temperature distribution as compared to the measured data.Both physics and implementation for the thermal simulation will be described. The code is applied to the analysis of a realistic design of CPU chip made of SOI technology with up to six metal interconnect layers. A comprehensive review of simulation results will be presented.
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 Additional Information
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Index Terms- thermal simulation, full chip, SOI, interconnect
Citation:
Zhiping Yu, Dan Yergeau, Robert W. Dutton, Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie,
"Full Chip Thermal Simulation,"
isqed,
p. 145,
First International Symposium on Quality of Electronic Design,
2000
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