| Abstract |
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The main problem of fractal image compression is the long search time of the domain pool. For this reason, the dedicated ASIC architecture for fractal image coding is needed. In this paper, we propose an efficient parallel architecture for fractal image coding which is based on fixed-size full-search algorithm. One of the main features of this architecture is that it uses only local communication such that each processor has a range and a domain block which is shifted to the next processor. Another main feature is that it has very regular interconnections and data flow. Domain blocks are formed from the range blocks in processors and the encoding procedure is performed by the regular data flow of domain blocks into the other processors. Each processor performs the fast isometric transformations which are calculated by one full rotation around the center.
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 Additional Information
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Index Terms- parallel architecture, VLSI architecture, systolic array, fractal image coding
Citation:
Shinhaeng Lee, Hirotomo Aso,
"A Parallel Architecture for High Speed Fractal Image Coding,"
ispan,
p. 88,
1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99),
1999
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