Abstract
This work presents a soft IP description of Rijndael, the Advanced Encryption Standard (AES) of National Institute of Standards and Technology (NIST). This Rijndael implementation run its symmetric cipher algorithm using a key size of 128 bits, mode called AES128. The focus here is to produce a low area IP achieving good performance. To do that, we propose a architecture using mixed bit size processing. The usage of memory has a significant decrease. The same methodology is used to implement three versions: the first one only encrypts the data, the second one decrypts and the third one performs both operation at same device. The implementation choice was Acex1K and Cyclone devices of Altera. The paper presents a introduction of cryptography, the AES contest that defined Rijndael as the new standard, the AES-128 structure and some results, such as device occupation, clock frequency, throughput and latency.