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Published Articles >> Table of Contents >> Abstract
32nd Annual International Symposium on Computer Architecture (ISCA'05)
pp. 186-196
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
Steven Balensiefer, University of Washington
Lucas Kregor-Stickles, University of Washington
Mark Oskin, University of Washington
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DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISCA.2005.10
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The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical implementation technology has progressed steadily. However, almost no work has yet been done which explores the architecture design space of large scale quantum computing systems. In this paper, we present a set of tools that enable the quantitative evaluation of architectures for quantum computers. The infrastructure we created comprises a complete compilation and simulation system for computers containing thousands of quantum bits. We begin by compiling complete algorithms into a quantum instruction set. This ISA enables the simple manipulation of quantum state. Another tool we developed automatically transforms quantum software into an equivalent, fault-tolerant version required to operate on real quantum devices. Next, our infrastructure transforms the ISA into a set of low-level micro architecture specific control operations. In the future, these operations can be used to directly control a quantum computer. For now, our simulation framework quickly uses them to determine the reliability of the application for the target micro architecture. Finally, we propose a simple, regular architecture for ion-trap based quantum computers. Using our software infrastructure, we evaluate the design trade offs of this micro architecture.
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Citation:
Steven Balensiefer, Lucas Kregor-Stickles, Mark Oskin,
"An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures,"
isca,
pp. 186-196,
32nd Annual International Symposium on Computer Architecture (ISCA'05),
2005
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